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eorex revision history revision 0.1 ( dec . 20 13 ) - first release em48 8 m32 44vb d dec. 2013 www.eorex.com 1/18
eorex em488m 32 44vbd 256 mb ( 2 m ? 4bank ? 32) synchronous dram features ? fully synchronous to positive clock edge ? single 3.3v ? 0.3v power supply ? lvttl compatible with multiplexed address ? programmable burst length (b/l) - 1, 2, 4, 8 or full page ? programmable cas latency (c/l) - 2 or 3 ? data mask (dqm) for read / write masking ? programmable wrap sequence C sequential (b/l = 1/2/4/8/full page) C interleave (b/l = 1/2/4/8) ? burst read with single - bit write operation ? all inputs are sampled at the rising edge of the system clock ? auto refresh and self refresh ? 4,096 refresh cycles / 64ms (15.625us) ordering information description the em488m 32 44vbd is synchronous dynamic random access memory (sdram) organized as 2 meg words x 4 banks by 32 bits. all inputs and outputs are s ynchronized with the positive edge of the clock. the 256m b sdram uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate at 3.3v low power memory system. it also provides auto refresh with power saving / down mode. all inputs and outputs voltage levels are compatible with lvttl. available packages: tfbga - 90b(13mmx8mm). * eorex reserves the right to change products or specification without notice. dec. 2013 www.eorex.com 2/ 18 part no organization max. freq package grade pb em488m3244vbd - 75 f 4m x 32 133mhz @cl3 tfbga - 90b commercial free em488m3244vbd - 75 f e 4m x 32 133mhz @cl3 tfbga - 90b extend temp. free part no organization max. freq package grade pb em488m3244vbd - 75f 8m x 32 133mhz @cl3 tfbga - 90b commercial free em488m3244vbd - 7f 8m x 32 143mhz @cl3 tfbga - 90b commercial free em488m3244vbd - 75 fe 8m x 32 133mhz @cl3 tfbga - 90b extend temp. free em488m3244vbd - 7fe 8m x 32 143mhz @cl3 tfbga - 90b extend temp. free em488m3244vbd - 75 f i 8m x 32 133mhz @cl3 tfbga - 90b industr i al temp. free em488m3244vbd - 7f i 8m x 32 143mhz @cl3 tfbga - 90b industr ial temp . free
eorex pin assignment em488m 32 44vbd 90ball tf bga / (13mm x 8mm) dec. 2013 www.eorex.com 3/18 1 2 3 7 8 9 dq26 dq24 vss a vdd dq23 dq21 dq28 vddq vssq b vddq vssq dq19 vssq dq27 dq25 c dq22 dq20 vddq vssq dq29 dq30 d dq17 dq18 vddq vddq dq31 nc e nc dq16 vssq vss dqm3 a3 f a2 dqm2 vdd a4 a5 a6 g a10 a0 a1 a7 a8 nc h nc ba1 a11 clk cke a9 j ba0 /cs /ras dqm1 nc nc k /cas /we dqm0 vddq dq8 vss l vdd dq7 vssq vssq dq10 dq9 m dq6 dq5 vddq vssq dq12 dq14 n dq1 dq3 vddq dq11 vddq vssq p vddq vssq dq4 dq13 dq15 vss r vdd dq0 dq2
pin description (simplified) eorex em488m 32 44vbd dec. 2013 www.eorex.com 4/18 pin name function j1 clk (system clock) master clock input (active on the positive rising edge) j8 /cs (chip select) selects chip when active j2 cke (clock enable) activates the clk when h and deactivates when l. cke should be enabled at least one cycle prior to new command. disable input buffers for power down in standby. g8,g9,f7,f3,g1, g2,g3,h1,h2,j3, g7,h9 a0~a11 (address) row address (a0 to a11) is determined by a0 to a11 level at the bank active command cycle clk rising edge. ca (ca0 to ca7) is determined by a0 to a7 level at the read or write command cycle clk rising edge. and this column address becomes burst access start address. a10 defines the pre - charge mode. when a10= high at the pre - charge command cycle, all banks are pre - charged. but when a10= low at the pre - charge command cycle, only the bank that is selected by ba is pre - charged. j7,h8 ba0,ba1 (bank address) selects which bank is to be active. j9 /ras (row address strobe) latches row addresses on the positive rising edge of the clk with /ras l. enables row access & pre - charge. k7 /cas (column address strobe) latches column addresses on the positive rising edge of the clk with /cas low. enables col umn access. k8 /we (write enable) latches column addresses on the positive rising edge of the clk with /cas low. enables column access. k9,k1,f8,f2 dqm0~dqm3 (data input/output mask) dqm controls i/o buffers. r8,n7,r9,n8,p9, m8,m7,l8,l2,m3, m2,p1,n2,r 1,n3, r2,e8,d7,d8,b9, c8,a9,c7,a8,a2, c3,a1,c2,b1,d2, d3,e2 dq0~dq31 (data input/output) dq pins have the same function as i/o pins on a conventional dram. a7,f9,l7,r7/ a3,f1,l3,r3 v dd /v ss (power supply/ground) v dd and v ss are power supply pins for inte rnal circuits. b2,b7,c9,d9,e1, l1,m9,n9,p2/b8, b3,c1,d1,e9,l9, m1,n1,p8 v ddq /v ssq (power supply/ground) v ddq and v ssq are power supply pins for the output buffers. e3,e7,h3,h7,k2, k3 nc (no connection) this pin is recommended to be left no connection on the device.
note: caution exposing the device to stress above those listed in absolute maximum ratings could capacit ance (v cc =3.3v, f=1mhz, t a =25c) recommended dc operating conditions (t a =0c ~70c) note: * all voltages referred to v ss . eorex absolute maximum rating em488m 32 44vbd cause permanent damage. the device is not meant to be operated under conditions outside the l imits described in the operational section of this specification. exposure to absolute maximum rating conditions for extended periods may affect device reliability. * v ih (max.) = 5.6v for pulse width 3ns * v il (min.) = - 2.0v for pulse width 3ns dec. 2013 www.eorex.com 5/18 symbol item rating units v in , v out input, output voltage - 0.5 ~ +4.6 v v dd , v ddq power supply voltage - 0.5 ~ +4.6 v t op operating temperature range commercial 0 ~ +70 c extended - 25 ~ +85 industrial - 40 ~ +85 t stg storage temperature range - 55 ~ +150 c p d power dissipation 1 w i os short circuit current 50 ma symbol parameter min. typ. max. units v dd power supply voltage 3.0 3.3 3.6 v v ddq power supply voltage (for i/o buffer) 3.0 3.3 3.6 v v ih input logic high voltage 2.0 v dd +0.3 v v il input logic low voltage - 0.3 0.8 v symbol parameter min. typ. max. units c clk clock capacitance 2.0 3.5 pf c i input capacitance for clk, cke, address, /cs, /ras, /cas, /we, dqml, dqmu 2.0 3.5 pf c o input/output capacitance 3.0 5.5 pf
(v dd =3.3v ? 0.3v, t a =0c ~70c , - 25c ~ +85c ) *all voltages referenced to v ss . recommended dc operating conditions (continued) eorex recommended dc operating conditions em488m 32 44vbd note 1: i cc1 depends on output loading and cycle rates. specified values are obtained with the output open. input signals are changed only one time during t ck (min.) note 2: i cc4 depends on output loading and cycle rates. specified values are obtained with the output open. input signals are changed only one time during t ck (min.) note 3: input signals are changed only one time during t ck (min.) note 4: standard power version. dec. 2013 www.eorex.com 6/18 symbol parameter test conditions max. units i cc1 operating current (note 1) burst length=1, t rc ? t rc (min.), i ol =0ma, one bank active 8 0 ma i cc2p precharge standby current in power down mode cke ? v il (max.), t ck =15ns 2 5 0 u a i cc2ps cke ? v il (max.), t ck = 20 0 u a i cc2n precharge standby current in non - power down mode cke ? v il (min.), t ck =15ns, /cs ? v ih (min.) input signals are changed one time during 30ns 1 6 ma i cc2ns cke ? v i l (min.), t ck = , input signals are stable 1 2 ma i cc3p active standby current in power down mode cke ? v il (max.), t ck =15ns 5 ma i cc3ps cke ? v il (max.), t ck = 4 ma i cc3n active standby current in non - power down mod e cke ? v il (min.), t ck =15ns, /cs ? v ih (min.) input signals are changed one time during 30ns 20 ma i cc3ns cke ? v il (min.), t ck = , input signals are stable 1 6 ma i cc4 operating current (burst mode) (note 2) t ccd ? 2clks, i ol =0ma 8 5 ma i cc5 refresh current (note 3) t rc ? t rc (min.) 1 15 ma i cc6 self refresh current cke ? 0.2v 4 50 (note 4) u a symbol parameter test conditions min. typ. max. units i il input leakage current 0 ? v i ? v ddq , v ddq =v dd all other pins not under test=0v - 1 +1 ua i ol output leakage current 0 ? v o ? v ddq , d out is disabled - 1.5 +1.5 ua v oh high level output voltage i o = - 2ma 2.4 v v ol low level output voltage i o =+2ma 0.4 v ?
eorex block diagram em488m 32 44vbd auto/self refresh counter a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 memory array dqm write dqm control data in a10 s/a & i/o gating doi a11 ba0 ba1 col. de coder col. add. buffer data out read dqm control mode register set col. add. counter burst counter timing register clk cke /cs /ras /cas /we dqm dec. 2013 www.eorex.com 7/18
(v dd =3.3v ? 0.3v, t a =0c ~70c) (v dd =3.3v ? 0.3v, t a =0c ~70c , - 25c ~ +85c ) * all voltages referenced to v ss . eorex ac operating test conditions em488m 32 44vbd ac operating test characteristics note 5: t hz defines the time at which the output achieve the open circuit condition and is not referenced to output voltage levels. dec. 2013 www.eorex.com 8/18 symbol parameter - 7 - 7.5 units min. max. min. max. t ck clock cycle time cl=3 7 7.5 ns cl=2 7.5 10 t ac access time form clk cl=3 5.5 5. 5 ns cl=2 5.5 6 t ch clk high level width 2.5 2.5 ns t cl clk low level width 2.5 2.5 ns t oh data - out hold time cl=3 3 3 ns cl=2 2 t h z data - out high impedance time (note 5) cl=3 3 7 3 7 ns cl=2 5.4 t lz data - out low impedance time 0 0 ns t ih input hold time 1 1 ns t is input setup time 1.5 1.5 ns item conditions output reference level 1.4v/1.4v output load see diagram as below input signal level 2.4v/0.4v transition time of input signals 2ns input reference level 1.4v
(v dd =3.3v ? 0.3v, t a =0c ~70c , - 25c ~ +85c ) * all voltages referenced to v ss . eorex em488m 32 44vbd ac operating test characteristics (continued) note 6: these parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing/clock period (count fractions as a whole number) recommended power on and initialization the following power o n and initialization sequence guarantees the device is preconditioned to each user s specific needs. (like a conventional dram) during power on, all v dd and v ddq pins must be built up simultaneously to the specified voltage when the input signals are held in the nop state. the power on voltage must not exceed v dd +0.3v on any of the input pins or v dd supplies. (clk signal started at same time) after power on, an initial pause of 200 s is required followed by a precharge of all banks using the precharge co mmand. to prevent data contention on the dq bus during power on, it is required that the dqm and cke pins be held high during the initial pause period. once all banks have been precharged, the mode register set command must be issued to initialize the mode register. a minimum of eight auto refresh cycles (cbr) are also required, and these may be done before or after programming the mode register. dec. 2013 www.eorex.com 9/18 symbol parameter - 7 - 75 un its min. max. min. max. t rc active to active command period (note 6) 6 2 67 ns t ras active to precharge command period (note 6) 4 2 45 1 0 0k ns t rp precharge to active command period (note 6) 20 20 ns t rcd active to read/write delay time (note 6) 20 20 ns t rrd active(one) to active(another) command (note 6) 1 4 15 ns t ccd read/write command to read/write command 1 1 clk t dpl date - in to precharge command 2 2 clk t bdl date - in to burst stop command 1 1 clk t roh data - out to high impe dance from precharge command cl=3 3 3 clk cl=2 2 2 t ref refresh time (4,096 cycle) 64 64 ms
se lf e ck h wr ite wit pr e se lf ex it e ck act t adbs e r ad re wit h e pr eorex simplified state diagram em488m 32 44vb d dec. 2013 www.eorex.com 10/18
address input for mode register set eorex em488m 32 44vbd dec. 2013 www.eorex.com 11/18 cas latency a6 a5 a4 reserved 0 0 0 reserved 0 0 1 2 0 1 0 3 0 1 1 reserved 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 burst length sequential inter leave a2 a1 a0 1 1 0 0 0 2 2 0 0 1 4 4 0 1 0 8 8 0 1 1 reserved reserved 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 full page reserved 1 1 1 ba1 ba0 a11 a10 a9 a8 a7 operation mode 0 0 0 0 0 0 0 normal 0 0 0 0 1 0 0 burst read with si ngle - bit write ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 operation mode cas latency bt burst length burst type a3 interleave 1 sequential 0
burst type (a3) * page length is a function of i/o organization and column addressing x 32 (ca0 ~ ca7): 1. command truth table h = high level, l = low level, x = high or low level (don't care), v = valid data input eorex em488m 32 44vbd full page = 256bits dec. 2013 www.eorex.com 12/18 burst length a2 a1 a0 sequential addressing interleave addressing 2 x x 0 01 01 x x 0 10 10 4 x 0 0 0123 0123 x 0 1 1230 1032 x 1 0 2301 2301 x 1 1 3012 3210 8 0 0 0 01234567 01234567 0 0 1 12345670 10325476 0 1 0 23456701 23016745 0 1 1 34567012 32107654 1 0 0 45670123 45670123 1 0 1 56701234 54761032 1 1 0 67012345 67452301 1 1 1 70123456 76543210 full page* n n n cn cn+1 cn+2 - command symbol cke /cs /ras /cas /we ba0, ba1 a10 a11, a9~a10 n - 1 n ignore command desl h x h x x x x x x no operation nop h x l h h h x x x burst stop bsth h x l h h l x x x read read h x l h l h v l v read with auto pre - charge reada h x l h l h v h v write writ h x l h l l v l v write with auto pre - charge writa h x l l h h v h v bank activate act h x l l h h v v v pre - charge select bank pre h x l l h l v l x pre - charge all banks pall h x l l h l x h x mode register set mrs h x l l l l l l v
2. dqm truth table h = high level, l = low level, x = high or low level (don't care), v = valid data input 3. cke truth table remark h = high level, l = low level, x = high or low level (don't ca re) eorex em488m 32 44vbd dec. 2013 www.eorex.com 13/18 item command symbol cke /cs /ras /cas /we addr. n - 1 n activating clock suspend mode entry h l x x x x x any clock s uspend mode l l x x x x x clock suspend clock suspend mode exit l h x x x x x idle cbr refresh command ref h h l l l h x idle self refresh entry self h l l l l h x self refresh self refresh exit l h l h h h x l h h x x x x idle power down entry h l x x x x x power down power down exit l h x x x x x upper byte write enable/output enable bsth h x l read read h x l read with auto pre - charge reada h x l write writ h x l write with auto pre - charge writa h x l bank activate act h x l pre - cha rge select bank pre h x l pre - charge all banks pall h x l mode register set mrs h x l data write/output enable enb h x h data mask/output disable mask h x l command symbol cke /cs n - 1 n
eorex 4. operative command table (note 7 ) remark h = high level, l = low level, x = high or low level (don't care) em488m 32 44vbd dec. 2013 www.eorex.com 14/18 current state /cs /r /c /w addr. command action idle h x x x x desl nop or power down (note 8) l h h x x nop or bst nop or power down (note 8) l h l h ba/ca/a10 read/reada illegal (n ote 9) l h l l ba/ca/a10 writ/writa illegal (note 9) l l h h ba/ra act row activating l l h l ba, a10 pre/pall nop l l l h x ref/self refresh or self refresh (note 10) l l l l op - code mrs mode register accessing row active h x x x x desl nop l h h x x nop or bst nop l h l h ba/ca/a10 read/reada begin read: determine ap (note 11) l h l l ba/ca/a10 writ/writa begin write: determine ap (note 11) l l h h ba/ra act illegal (note 9) l l h l ba, a10 pre/pall pre - charge (note 12) l l l h x r ef/self illegal (note 10) l l l l op - code mrs illegal read h x x x x desl continue burst to end ? row active l h h h x nop continue burst to end ? row active l h h l x bst burst stop ? row active l h l h ba/ca/a10 read/reada terminate burst, new read: determine ap (note 13) l l l l ba/ca/a10 writ/writa terminate burst, start write: determine ap (note 13, 14) l l h h ba/ra act illegal (note 9) l l h l ba, a10 pre/pall terminate burst, pre - charging (note 10) l l l h x ref/self illegal l l l l op - code mrs illegal write h x x x x desl continue burst to end ? write recovering l h h h x nop continue burst to end ? write recovering l h h l x bst burst stop ? row active l h l h ba/ca/a10 read/reada terminate burst, start read: determine a p 7, 8 (note 13, 14) l l l l ba/ca/a10 writ/writa terminate burst, new write: determine ap 7 (note 13) l l h h ba/ra act illegal (note 9) l l h l ba, a10 pre/pall terminate burst, pre - charging (note 15) l l l h x ref/self illegal l l l l op - code mrs illegal
4. operative command table (continued) (note 7 ) remark h = high level, l = low level, x = high or low level (don't care), ap = aut o pre - charge eorex em488m 32 44vbd dec. 2013 www.eorex.com 15/18 current state /cs /r /c /w addr. command action read with ap h x x x x desl continue burst to end ? pre - charging l h h h x no p continue burst to end ? pre - charging l h h l x bst illegal l h l h ba/ca/a10 read/reada illegal (note 9) l h l l ba/ca/a10 writ/writa illegal (note 9) l l h h ba/ra act illegal (note 9) l l h l ba, a10 pre/pall illegal (note 9) l l l h x ref/ self illegal l l l l op - code mrs illegal write with ap h x x x x desl burst to end ? write recovering with auto pre - charge l h h h x nop continue burst to end ? write recovering with auto pre - charge l h h l x bst illegal l h l h ba/ca/a10 read/re ada illegal (note 9) l h l l ba/ca/a10 writ/writa illegal (note 9) l l h h ba/ra act illegal (note 9) l l h l ba, a10 pre/pall illegal (note 9) l l l h x ref/self illegal l l l l op - code mrs illegal pre - charging h x x x x desl nop ? enter idle after t rp l h h h x nop nop ? enter idle after t rp l h h l x bst illegal l h l h ba/ca/a10 read/reada illegal (note 9) l h l l ba/ca/a10 writ/writa illegal (note 9) l l h h ba/ra act illegal (note 9) l l h l ba, a10 pre/pall nop ? enter idle af ter t rp l l l h x ref/self illegal l l l l op - code mrs illegal row activating h x x x x desl nop ? enter idle after t rcd l h h h x nop nop ? enter idle after t rcd l h h l x bst illegal l h l h ba/ca/a10 read/reada illegal (note 9) l h l l ba/ ca/a10 writ/writa illegal (note 9) l l h h ba/ra act illegal (note 9, 16) l l h l ba, a10 pre/pall illegal (note 9) l l l h x ref/self illegal l l l l op - code mrs illegal
4. operative command table (continued) (note 7 ) remark h = high level, l = low level, x = high or low level (don't care), ap = auto pre - charge eorex em488m 32 44vbd note 7: all entries assume that cke was active (high level) during the preceding clock cycle. note 8: if all banks are idle, and cke is inactive (low level), sdram will ente r power down mode. all input buffers except cke will be disabled. note 9: illegal to bank in specified states; function may be legal in the bank indicated by bank address (ba), depending on the state of that bank. note 10: if all banks are idle, and cke is inactive (low level), sdram will enter self refresh mode. all input buffers except cke will be disabled. note 11: illegal if t rcd is not satisfied. note 12: illegal if t ras is not satisfied. note 13: must satisfy burst interrupt condition. note 14: must s atisfy bus contention, bus turn around, and/or write recovery requirements. note 15: must mask preceding data which don't satisfy t dpl . note 16: illegal if t rrd is not satisfied. dec. 2013 www.eorex.com 16/18 current state /cs /r /c /w addr. command action write recovering h x x x x desl nop ? enter row active after t dpl l h h h x nop nop ? enter row active after t dpl l h h l x bst nop ? enter row active after t dpl l h l h ba/ca/a10 read/reada start read, determine ap l h l l ba/ca/a10 writ/writa new write, determine ap (note 14) l l h h ba/ra act illegal (note 9) l l h l ba, a10 pre/pall illegal (note 9) l l l h x ref/self illegal l l l l op - code mr s illegal write recovering with ap h x x x x desl nop ? enter pre - charge after t dpl l h h h x nop nop ? enter pre - charge after t dpl l h h l x bst nop ? enter pre - charge after t dpl l h l h ba/ca/a10 read/reada illegal (note 9, 14) l h l l ba/ca/a1 0 writ/writa illegal (note 9) l l h h ba/ra act illegal (note 9) l l h l ba, a10 pre/pall illegal l l l h x ref/self illegal l l l l op - code mrs illegal refreshing h x x x x desl nop ? enter idle after t rc l h h x x nop/bst nop ? enter idle aft er t rc l h l x x read/writ illegal l l h x x act/pre/pall illegal l l l x x ref/self/mrs illegal mode register accessing h x x x x desl nop l h h h x nop nop l h h l x bst illegal l h l x x read/writ illegal l l x x x act/pre/pall/ ref/self /mrs illegal
5. command truth table for cke remark: h = high level, l = low level, x = high or low level (d on't care) eorex em488m 32 44vbd notes 17: self refresh can be entered only from the both banks idle state. power down c an be entered only from both banks idle or row active state. notes 18: must be legal command as defined in operative command table dec. 2013 www.eorex.com 17/18 current state cke /cs /r /c /w addr. actio n n - 1 n self refresh h x x x x x x invalid, clk(n - 1) would exit self refresh l h h x x x x self refresh recovery l h l h h x x self refresh recovery l h l h l x x illegal l h l l x x x illegal l l x x x x x maintain self refresh self refresh recovery h h h x x x x idle after t rc h h l h h x x idle after t rc h h l h l x x illegal h h l l x x x illegal h l h x x x x illegal h l l h h x x illegal h l l h l x x illegal h l l l x x x illegal power down h x x x x x x invalid, clk(n - 1) would exit power down l h x x x x x exit power down ? idle l l x x x x x maintain power down mode both banks idle h h h x x x refer to operations in operative command table h h l h x x h h l l h x h h l l l h x refresh h h l l l l op - code refer to operations in operative command table h l h x x x h l l h x x h l l l h x h l l l l h x self refresh (note 17) h l l l l l op - code refer to operations in operative command table l x x x x x x power down (note 17) r ow active h x x x x x x refer to operations in operative command table l x x x x x x power down (note 17) any state other than listed above h h x x x x refer to operations in operative command table h l x x x x x begin clock suspend next cycle (note 18) l h x x x x x exit clock suspend next cycle l l x x x x x maintain clock suspend
eorex package description em488m 32 44vbd dec. 2013 www.eorex.com 18/18

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